🧲 Core Memory Lab

Coincident-current ferrite core RAM — the memory that ran computing from ~1953 to the late 1970s

What is core memory?

Before silicon chips, computers stored bits in tiny donut-shaped ferrite magnets (cores), each about 0.3–2 mm across, threaded on a grid of fine wires. Each core stores one bit as the direction of its magnetization — and keeps it forever, with no power.

This lab simulates a miniature machine: 8 planes × 8×8 cores = 64 bytes. Real planes were typically 64×64 = 4,096 cores, stacked 8–36 planes deep.

The four key ideas

  • Square hysteresis loop. Ferrite is a switchable permanent magnet: pulse current one way → “1”, the other way → “0”. Between pulses it sits at remanence ±Br — that’s why it’s non-volatile.
  • Coincident-current selection. Each core is threaded by one X and one Y wire. A ½-current can't flip a core (below the coercive threshold). Only the core where the chosen X and Y cross feels ½I + ½I = full I — selecting 1 core out of thousands with no electronics per core.
  • Reading destroys the data. A read drives the selected cores toward 0. If a core was holding 1, it flips, and the sudden flux change induces a pulse on a sense wire threaded through every core of the plane. Pulse = “it was a 1”. Afterwards the bit is gone — so every read is followed by an automatic restore (write-back).
  • The inhibit wire writes zeros. On write, X and Y try to write 1 everywhere in the word. Planes that must store 0 fire a fourth wire carrying an opposing ½I that cancels the drive at the selected core: net ½I, no flip.

Historical context

1949An Wang files the patent for magnetic pulse transfer devices — the seed of core memory.

1951Jay Forrester’s team at MIT invents coincident-current addressing for the Whirlwind computer.

1953Whirlwind runs the first working core memory. It is ~2× faster and vastly more reliable than Williams tubes and delay lines.

1955Core goes commercial: IBM 704/705. Soon every serious machine uses it — SAGE’s AN/FSQ-7 carries 256K+ bytes.

1964IBM System/360 standardizes on core; a typical cycle takes ~1 µs.

1966–72The Apollo Guidance Computer flies 2K words of erasable core (plus “core rope” ROM woven to store software). Core’s non-volatility and radiation tolerance make it ideal for space.

1970Intel’s 1103 1-kilobit DRAM chip arrives. Semiconductor RAM is cheaper, denser, and needs no restore cycle.

~1980Core fades from mainstream use — but the Space Shuttle’s IBM AP-101 still flew core memory until a 1991 upgrade.

todayThe legacy lives on in the phrase “core dump.”

How it was built

Cores were too small for machines to thread: planes were woven by hand, under microscopes, largely by skilled women workers recruited from the textile and garment industries — insiders jokingly called it “LOL memory” (little old ladies). A sense wire had to pass through thousands of cores without a single mistake. Prices fell from ~$1/bit in the 1950s to pennies per bit by the 1970s.

Suggested tour

  • One Core — play with the physics: pulses, the hysteresis loop, half-selects, power loss. Watch the magnetic domains flip inside the ferrite and the sense-wire pulse on the scope.
  • Memory — the full stack: see all 8 planes work at once, tap a core, then STEP through a read–restore cycle; watch the B-H loop and the half-selected neighbors.
  • Circuits — the electronics: decoders, drivers, sense amp, inhibit. Tap blocks, animate a cycle.
  • Programs — watch 1950s-style software: self-modifying code and read-modify-write counters running on this very memory — every fetch and store animates a physical core cycle through the stack.
  • Tip: tap 🔈 in the header for machine sounds — drive pulses, sense pings and the strobe.

One core, up close

A single ferrite toroid with a drive wire and a sense wire. Its state lives on a square hysteresis (B–H) loop: current H pushes the operating point around the loop; when current stops it relaxes to remanence — top (“1”) or bottom (“0”). Dashed lines are the ½-select threshold: a half-current never crosses them, so the core can’t flip.

Inside the ferrite, tiny magnetic domains hold the bit — watch them all swing around when the core flips. The green strip below is an oscilloscope on the sense wire: voltage is induced only while flux is changing (dB/dt), which is exactly how a read detects a stored 1.

State: 1

The core sits at remanence +Br. Nothing is powered, yet the bit is stored — it’s a permanent magnet.

A core stack: 8 bit-planes (b0–b7) make 64 eight-bit words. One X and one Y wire run through all planes, so one address selects a whole word at once. Tap a core below to pick an address, then run a cycle — or flip to Edit mode to write bits directly.

The whole stack, live. One X and one Y wire thread all 8 planes, so a single address lights one core in every plane — one full word (bit ladder on the right). Lime rings = sense pulses, pink planes = inhibited, ½-select current animates along the wires.
X drive Y drive sense inhibit ½ = half-selected (won’t flip)
Idle
SENSE STROBE INHIBIT
MEMORY DATA REGISTER
Tap any core to select a word address, then press READ or WRITE and use STEP / PLAY to walk through the cycle.
DATA TO WRITE (tap bits)

The electronics around the stack. Tap any block for an explanation, or animate a full read–restore cycle and watch the signal flow (dashed purple = timing/control).

TIMING & CONTROLread pulse → strobe → write pulse ADDRESS REGMAR · 6 bits X DECODER1 of 8 Y DECODER1 of 8 X DRIVERS½I switches Y DRIVERS½I switches CORE PLANE 8×8one bit-plane (real: 64×64 = 4096)sense wire threads all cores8 stacked planes = 64 bytes SENSE AMP+ strobe gate DATA REGMDR · 8 bits INHIBIT DRIVERSgated by MDR bits = 0
How it fits together

Tap a block above. The CPU never touches cores directly: it loads an address into the MAR and data into the MDR, and the timing generator runs the whole read–restore sequence automatically.

Classic algorithms running on this very memory (shared with the Memory tab). Every fetch, load and store below secretly executes a full read–restore cycle — watch it happen physically in the stack. Look for ◈ self-modifying instructions — before index registers, programs rewrote themselves, and core memory made that easy.

PC
00
A
00
MAR
00
MDR
00
Z flag
0
CYCLES ≈ µs
0

The stack, executing

Every fetch, load and store is a physical read–restore cycle: the word’s cores collapse to 0, sense pulses fire on the planes that held 1s (lime rings), then the restore/write puts the bits back — the inhibit (pink planes) holds the zeros. On a 1960s machine each of these took ≈1 µs.

Memory — 64 bytes (green = read, amber = written · bit strip below each byte)

tap a cell, adjust value

Program (8-bit words: 2-bit op + 6-bit addr)

Press STEP to execute one micro-operation.