4004

Four wires, eight beats

The 4004 has a single 4-bit bus, D0–D3, shared by addresses, instructions and data. A machine cycle is eight clock periods: during A1–A3 the CPU sends its 12-bit program counter out as three nibbles; during M1–M2 the selected 4001 ROM returns the 8-bit instruction word as two nibbles; during X1–X3 the CPU executes, possibly exchanging one more nibble with RAM or a port. At the full 740 kHz clock that is 10.8 µs per instruction word — about 92,600 single-word instructions per second.

Registers and the stack

Beside the 4-bit accumulator and carry there are sixteen 4-bit index registers, R0–R15, pairable into eight 8-bit pairs P0–P7 for constants (FIM), indirect ROM access (FIN, always via R0R1) and address latching (SRC). The program counter is one of four 12-bit registers; the other three form a pushdown stack, so subroutines can nest exactly three deep. There is no overflow trap — a fourth JMS silently overwrites the oldest return address, a fact 4004 programmers learned to respect.

How SRC addresses the world

I/O and RAM instructions carry no operand. Instead, SRC latches a register pair into every memory chip in the system, and each chip decodes the part it cares about:

SRC byte  C C R R N N N N
           │ │  │ │   └────── data character 0–F
           │ │  └─┴────────── RAM register 0–3
           └─┴─────────────── 4002 chip 0–3 within the bank

for ROM I/O (WRR / RDR): high nibble C C R R = 4001 chip number 0–F

DCL then selects which of up to eight CM-RAM banks the next RAM instruction talks to. A fully-loaded system reaches 16 ROMs (4 KB of program) and dozens of 4002s — this simulator models all 8 banks × 4 chips.

Inside a 4002

Each 4002 holds four registers of 16 data characters plus 4 status characters (320 bits), and drives one 4-bit output port. The odd-looking status characters are pure calculator DNA: in the Busicom firmware they held a number's sign, decimal-point position and overflow digits while the sixteen data characters held its mantissa. WRM/RDM touch data; WR0–3/RD0–3 touch status; WMP drives the port that, in 1971, switched printer hammers and lamps.

Pages

Program memory is divided into 256-byte pages. JCN and ISZ carry only 8 address bits, so they jump within the page of the following instruction; FIN and JIN read within the current page (an instruction sitting on a page's last word uses the next page — a genuine 4004 quirk this simulator reproduces). Only JUN and JMS carry a full 12-bit address.

What this simulator models

Everything architecturally visible: the complete instruction set with real carry/borrow semantics (SUB and SBM subtract with borrow, DAA leaves carry alone when it doesn't overflow, DAC signals borrow with CY = 0, KBP encodes the Busicom keypad), the 3-level stack, page-limited jumps, SRC/DCL addressing, ROM ports, RAM data/status/ports, the TEST pin, and per-word cycle counting at 740 kHz. Not modelled: sub-cycle bus signals (SYNC, CM lines as waveforms) and WPM, which needed the 4008/4009 program-RAM companions. Two idioms worth knowing: ISZ jumps while its register is non-zero, so a counter loaded with 16 − N loops N times; and JUN to itself is the conventional halt, which the simulator detects and stops on.

In the summer of 1969, a Japanese calculator company called Busicom brought Intel — then a year-old memory-chip startup — a contract design for its 141-PF printing calculator: roughly a dozen custom logic chips, each wired for one job. Ted Hoff, Intel employee number 12, thought the plan was too complex to build profitably and proposed something heretical instead: shrink the design to a handful of chips by making one of them a general-purpose, program-driven processor and putting the calculator's personality in ROM. Stan Mazor helped Hoff work the idea into an architecture and instruction set, and Busicom's engineer Masatoshi Shima — who would later co-design the 8080 and Z80 — refined the logic and wrote the calculator firmware that would run on it.

The proposal sat as paper until April 1970, when Intel hired Federico Faggin from Fairchild. Faggin had invented commercial silicon-gate MOS technology, and it was exactly the ingredient the paper design needed: silicon gates packed transistors densely enough, and switched fast enough, to fit a whole CPU into a 16-pin package. In nine months he turned the architecture into working silicon, inventing his own methodology for random-logic MOS design as he went and etching his initials — F.F. — into the corner of the die. The first wafer run in December 1970 came back dead: a masking layer had been left out. The corrected run in early 1971 worked essentially perfectly, and Busicom's 141-PF went on sale with a 4004 inside.

Intel's masterstroke was contractual. Busicom, under price pressure, asked for a discount; Intel returned about $60,000 and in exchange won the right to sell the chip set to anyone for anything except calculators. On November 15, 1971, a full-page ad in Electronic News announced the MCS-4 family and a new era of integrated electronics — a CPU you could buy off the shelf for $60. The claim looked like advertising copy; it turned out to be an understatement. Roughly ENIAC's computing power — thirty tons of machine in 1946 — now occupied 3 × 4 millimetres of silicon.

The lineage runs straight from this die to the present: the 4040 refined it, the 8008 and 8080 carried the idea to 8 bits (with Faggin and Shima again), Faggin left to found Zilog and build the Z80, and the 8086 that followed at Intel began the x86 line still running most of the world's desktops and servers. Every one of them keeps the 4004's basic shape: fetch on a shared bus, decode, execute through an accumulator and flags — the very loop animated above.

The MCS-4 family